Referring to FIG. 1, a conventional quad flat no-lead (QFN) lead frame includes an outer frame 11, a metallic die pad 12 surrounded by the outer frame 11, a connecting portion 13 connected to the metallic die pad 12 and the outer frame 11, and a plurality of spaced-apart leads 14 that extend from the outer frame 11 toward the metallic die pad 12 and that are spaced-apart from the metallic die pad 12. Referring to FIG. 2, when the conventional QFN lead frame is packaged, a chip 100 is first disposed on the metallic die pad 12, and then a plurality of wires 15 are connected to the chip 100 and the spaced-apart leads 14. Finally, the chip 100 and the outer frame 11 are covered by a polymeric encapsulating material, followed by curing the polymeric encapsulating material to form a polymeric encapsulating layer 16, thereby obtaining a conventional chip packaging device.
However, considering that the operability of the packing process and poor adhesion strength between the polymeric encapsulating layer 16 and the metallic die pad 12 may adversely affect reliability and performance of the chip packaging device, a ratio of an area of a surface of the chip 100 attached to the metallic die pad 12 to an area of a surface of the metallic die pad 12 for disposing the chip 100 is generally controlled by reducing heterogeneous interfaces between the polymeric encapsulating layer 16 and the metallic die pad 12. However, there is still a room for improving adhesion strength between the polymeric encapsulating layer 16 and the metallic die pad 12 in the conventional chip packaging device.